The Q-flag in the program status register (PSR) indicates which of the following?
In a multi-processor system, there are four processors numbered 0, 1, 2 and 3. The state of the processors is as follows:
CPU 2 executes a SEV instruction. What is the effect on the system?
In an ARMv7-A processor, which control register is used to enable the Memory Management Unit (MMU)?
Which power mode describes the state where the ARM processor is powered down, but its Level 1 caches remain powered?
In a Cortex-A processor, assume an initial value of R1 =0x80004000.
If the following instruction causes a data abort, what value will R1 contain on entry to the abort handler?
LDR R0, [R1, #8]!
Which of the following ARM processors has the best energy efficiency (measured in mW/MHz)?
On a processor supporting the Security Extensions, what sequence of operations is required to move from Non-secure User mode to Secure state?
An Advanced SIMD intrinsic has the prototype:
uint8xl6x2_t vld2q_u8 (uint8_t const * ptr);
How many bytes does this intrinsic load from memory?
Which of the following best describes the relationship between Tightly Coupled Memories (TCM), Level 1 (L1) and Level 2 (L2) cache memory systems?
The following pseudocode sequence shows a flag being set to indicate that new data is ready to be read by another thread:
data = 123;
ready = true;
Assuming that the reader threads may execute on any other core of a multicore system, which of the following is the most efficient memory barrier to place between the two writes to prevent them being observed in the opposite order?
Which TWO of the following options are DISADVANTAGES of building source code to use software floating point? (Choose two)
In an ARMv7-A processor, with which level of the memory system is the Memory Management Unit (MMU) associated?
In the Generic Interrupt Controller (GIC) architecture, which of the following ID numbers are reserved for interrupts that are private to a CPU interface?
Which one of the following statements best describes the function of vector catch logic?
Assuming a 4-core Cortex-A9 SMP system which does not use the Accelerator Coherency Port (ACP). and operates the L1 caches in writeback mode, in which of the following situations is a cache clean operation required?
A deeply embedded real-time industrial control system is missing some hard real-time interrupt deadlines. Which of the following performance analysis techniques is the most suitable for identifying which routines are causing the problem?
In which of the following scenarios would cache maintenance operations be necessary in an ARMv7 system?
Which of the following statements is TRUE with respect to the power consumption related to memory accesses?
An undefined instruction will cause an Undefined Instruction exception to be taken when:
The following pair of functions implement a simple mutex spinlock which might be used to protect a critical code section in a multi-threaded application. The address of the lock variable is in r0.
In order to minimize power while waiting for the lock to be available. SEV and WFE instructions can be used to place the processor in a low power state while waiting for the lock to become available. At which points should these instructions be placed?
Which of the following features was added in version 2 of the ARM Architecture Advanced SIMD extensions?
Which TWO of the following accurately describe constraints on the location of the Tightly Coupled Memory (TCM) regions in a Cortex-R4 processor? (Choose two)
When programming in C, how many bytes of stack are needed to pass parameters when calling the following function?
int foo( int arg_a, int arg_b, int arg_c )
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TESTED 26 Apr 2024
